Video switching detecting circuit

ABSTRACT

The object of the invention is to provide a video switchover detection circuit that reduces the circuit scale and allows high-accuracy detection with a smaller-scale configuration.  
     According to the invention, the video switchover detection circuit comprises a PLL circuit composed of a phase comparator, an LPF, a VCO, and a frequency divider. In the phase comparator, the phase of an external HD as an input signal obtained by shaping the pulse of a horizontal synchronization signal is compared with the phase of an internal HD as a reference signal obtained by dividing the frequency of the output pulse of the VCO in the PLL circuit. In case the phases of the signals differ from each other, an error signal is output from the phase comparator. A first counter counts the period in which the error signal is active, or the time when the phase difference persists. A horizontal synchronization decision section determines the lock state of the horizontal synchronization signal depending on the length of the phase difference duration and in case out of synchronization is detected, a video switchover detection signal is output from an output circuit.

TECHNICAL FIELD

[0001] The present invention relates to apparatus for inputting a videosignal for example from a video camera and performing signal processingand recording, and in particular to a video switchover detection circuitthat uses a phase-locked loop circuit.

BACKGROUND OF THE INVENTION

[0002] Conventionally, a method for detection of video switchover bydetecting out of lock of a phase-locked loop circuit (hereinafterreferred to as a PLL circuit) by using a PLL circuit, as a method fordetecting switchover of video signals. Such methods for detecting out oflock of a PLL circuit includes a method for monitoring a voltage(hereinafter referred to as a VCO control voltage) to be applied tocontrol a voltage-controlled oscillator (hereinafter referred to as aVCO) The VCO control voltage is typically an output of a low-passfilter. The low-pass filter includes a capacitor so thatre-charging/discharging of the low-pass filter takes time and not fitfor apparatus that requires high-speed operation. In order to offsetthis disadvantage, methods have been proposed for detecting thedislocation amount of a synchronization signal for an input signalagainst a reference signal and detecting out of lock based on thedislocation amount of the phase, as described in the Japanese PatentLaid-Open No. 55161/1998 and the Japanese Patent Laid-Open No.301526/1998.

[0003]FIG. 5 is a block diagram showing an configuration example of arelated art video switchover detection circuit. The video switchoverdetection circuit comprises a phase comparator 51, a low-pass filter(hereinafter referred to as an LPF) 52, a voltage-controlled oscillator(hereinafter referred to as a VCO) 53, and a frequency divider 54, andconstitutes a PLL circuit with these circuits 51 through 54. As inputsignals, an external HD that is a pulse obtained by extracting andshaping a horizontal synchronization signal for a video signal and anexternal VD obtained by extracting and shaping a verticalsynchronization signal are input. In the description that follows, acircuit that detects out of lock in the horizontal synchronizationsignal is called an H system and a circuit that detects out of lock inthe vertical synchronization signal is called a V system.

[0004] For each of the H and V systems, there are provided reset signalgenerating circuit 55, 59, counters 56, 60, window setting circuits, 57,61 and decision circuits 58, 62, respectively. The window settingcircuit 57 and the decision circuit 58 compose an H systemsynchronization decision section 63. The window setting circuit 61 andthe decision circuit 62 compose an V system synchronization decisionsection 64. Further, there is provided an output circuit 65 composed ofan OR circuit that outputs as a video switchover detection signal theoutput of the synchronization decision sections 63, 64.

[0005] In the PLL circuit, the output of a phase comparator 51 is inputto the VCO 53 via the LPF 52 to cause the VCO 53 to oscillate. Theoscillation signal obtained is multiplied by 1/N by using the frequencydivider 54 to generate an internal HD serving as a reference signal.

[0006] To detect out of lock in the horizontal synchronization signal,the output pulses of the VCO 53 are counted as a clock by the counter56, and the lock state of the horizontal synchronization signal isdetermined by the synchronization decision section 63 based on thecounter value of the counter 56. In this practice, the internal HD andthe output of the VCO 53 are input to the reset signal generatingcircuit 55. A reset signal is generated based on the correspondingsignal timings and input to the reset terminal of the counter 56. As aresult, the counter 56 is reset based on the timing of the internal HD.The output pulses of the VCO 53 are counted by the counter 56 and thecounter value is input to the synchronization decision section 63.

[0007] In the synchronization decision section 63, the window settingcircuit 61 sets the window period for determining the lock state and thedecision circuit 58 references the count value at the leading edge ofthe external HD and determined whether the timing at the leading edge ofthe external HD is within a predetermined widow period in relation tothe internal HD. The synchronization decision section 63 detects thedislocation amount of the external HD against the internal HD. In casethe dislocation amount has exceeded a predetermined value, thehorizontal synchronization signal is assumed as out of synchronizationand an out-of-lock detection signal is output.

[0008] To detect out of lock in the vertical synchronization signal, thelock state is determined same as the horizontal synchronization signal.That is, output pulses of the frequency divider 54 are counted as aclock by the counter 60, and the lock state of the verticalsynchronization signal is determined by the synchronization decisionsection 64 based on the counter value of the counter 60. In thispractice, the internal HD and the external HD are input to the resetsignal generating circuit 59. A reset signal is generated based on thecorresponding signal timings and input to the reset terminal of thecounter 60. As a result, the counter 60 is reset based on the timings ofthe internal HD and the external HD. The internal HD is the counted bythe counter 60 and the counter value is input to the synchronizationdecision section 64. Output pulses of the VCO 53 may be counted inparallel by the counter 60.

[0009] In the synchronization decision section 64, the window settingcircuit 61 sets the window period for determining the lock state and thedecision circuit 62 references the count value at the leading edge ofthe external VD and determined whether the timing at the leading edge ofthe external VD is within a predetermined widow period in relation tothe internal HD. In case the synchronization decision section 64 hasdetected that the timing of the external VD against the internal HDexceeded a predetermined range, the synchronization decision section 64assumes that the vertical synchronization signal is out ofsynchronization and outputs an out-of-lock detection signal.

[0010] In case the H-system or V-system out-of-lock detection signal isoutput, it is determined that the video signal input is switched overand the horizontal or-vertical synchronization signal has gone out ofsynchronization. At this time, a video switchover detection signal isoutput from the output circuit 65. In this way, detection of videoswitchover is performed based on the lock state of the horizontal orvertical synchronization signal.

[0011] In the aforementioned related art video switchover detectioncircuit, in order to detect the phase dislocation amount of asynchronization signal against the internal HD as a reference signal, awindow is set to determine whether the timing at the leading or trailingedge of an input signal is within the window period. Thus, a windowsetting circuit or a counter with a large-scale circuit is required tocount the clock over the window period. This resulted in a complicatedand large-scale circuit configuration. For example, in detectingH-system out of lock, a counter for counting the window period needssome 10 bits because the timing of the external HD may be earlier thanthat of the internal HD. A large number of count value is required inorder to determine out of lock thus taking time to determine out oflock.

[0012] The invention has been proposed in consideration of theaforementioned circumstances and aims at providing a video switchoverdetection circuit that reduces the circuit scale and allowshigh-accuracy detection with a smaller-scale configuration.

DISCLOSURE OF THE INVENTION

[0013] The first aspect of the invention is a video switchover detectioncircuit comprising a phase-locked loop circuit for comparing the phaseof an input signal with that of an oscillating signal that is based onthe input signal to perform phase synchronization, said video switchoverdetection circuit detecting switchover of input video signals by using asynchronization signal for a video signal used as said input signal anda reference signal that is based on said oscillating signal,characterized in that said video switchover detection circuit comprisesphase comparison means for comparing the phase of a horizontalsynchronization signal for said video signal with that of said referencesignal, phase difference count means for starting to count time when aphase difference has occurred between both signals based on said phasecomparison results and counting the period in which the phase differencepersists, horizontal synchronization decision means for determining outof synchronization of said video signal in the horizontal direction incase the count value has exceeded a predetermined decision value basedon the count value of said phase difference count means, and detectionoutput means for outputting a video switchover detection signalindicating switchover of video signals based on the output of saidhorizontal synchronization decision means.

[0014] The second aspect of the invention is a video switchoverdetection circuit according to the invention characterized in that saidphase comparison means outputs an error signal that goes active andindicates phase dislocation when the phase of a horizontalsynchronization signal for said video signal differs from that of saidreference signal and that said phase difference count means counts theclock of said oscillating signal in the period in which the error signalis active thus counting the period in which phase difference persistswhen said error signal is input to the enable terminal.

[0015] The third aspect of the invention is a video switchover detectioncircuit according to the invention comprising horizontal synchronizationcount means for counting the reference signal corresponding to thehorizontal synchronization signal for said video signal and verticalsynchronization decision means for determining out of synchronization ofsaid video signal in the vertical direction based on the count value ofsaid horizontal synchronization count means in case the count valueobtained when the vertical synchronization signal for said video signalis input is below a specified decision value, characterized in that saiddetection output means outputs a video switchover detection signalindicating switchover of video signals based on the output of saidhorizontal synchronization decision means and said verticalsynchronization decision means.

[0016] The fourth aspect of the invention is a video switchoverdetection circuit according to the invention comprising a phase-lockedloop circuit for comparing the phase of an input signal with that of anoscillating signal that is based on the input signal to perform phasesynchronization, said video switchover detection circuit detectingswitchover of input video signals by using a synchronization signal fora video signal used as said input signal and a reference signal that isbased on said oscillating signal, characterized in that said videoswitchover detection circuit comprises horizontal synchronization countmeans for counting the horizontal synchronization signal for said videosignal, vertical synchronization decision means for determining out ofsynchronization of said video signal in the vertical direction based onthe count value of said horizontal synchronization count means in casethe count value obtained when the vertical synchronization signal forsaid video signal is input is below a specified decision value, anddetection output means for outputting a video switchover detectionsignal indicating switchover of video signals based on the output ofsaid vertical synchronization decision means.

[0017] In the aforementioned configuration, in the horizontal directionof the video signal, the phase of a horizontal synchronization signal iscompared with that of a reference signal that is based on theoscillating signal of a phase-locked loop circuit. In case the phase ofthe horizontal synchronization signal differs from that of the referencesignal, the duration the phase difference persisted is counted by thephase difference count means. In the vertical direction of the videosignal, the reference signal corresponding to said horizontalsynchronization signal, or the number of horizontal scanning lines inthe video signal is counted frame by frame by the horizontalsynchronization count means. Then it is determined whether the countvalue obtained when said synchronization signal is input is below apredetermined value, or whether the signal has changed over in themiddle of a frame thus detecting video switchover.

[0018] This allows detection of video switchover by determining out ofsynchronization by using a small count value, thereby reducing thecircuit scale of the count means. It is possible to simplify anddownsize the configuration of the synchronization decision means thusproviding accurate and easy video switchover. This also reduces the timerequired for counting for out-of-synchronization detection therebyreducing the time required to detect video switchover.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a block diagram showing the configuration of a videoswitchover detection circuit according to an embodiment of theinvention;

[0020]FIG. 2 is a timing chart showing the out-of-lock detectionoperation in the H system in the embodiment;

[0021]FIG. 3 is a timing chart showing the out-of-lock detectionoperation in the V system in the embodiment;

[0022]FIG. 4 is a block diagram showing the exemplary configuration ofvideo monitoring apparatus as an application example of a video signalswitchover detection circuit;

[0023]FIG. 5 is a block diagram showing the exemplary configuration of arelated art video switchover detection circuit.

[0024] In the figures, a numeral 1 represents a phase comparator, 2 alow-pass filter (LPF), 3 a voltage-controlled oscillator (VCO), 4 afrequency divider, 5, 10 reset signal generating circuits, 6 a firstcounter, 7, 12 decision value setting circuits, 8, 13 decision circuits,9 horizontal synchronization decision section, 11 a second counter, 14 avertical synchronization decision section, and 15 an output circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0025] The embodiment of the invention will be described referring tothe drawings.

[0026]FIG. 1 is a block diagram showing the configuration of a videoswitchover detection circuit according to the embodiment of theinvention. FIGS. 2 and 3 are timing charts showing the operation in theembodiment.

[0027] The video switchover detection circuit comprises a phase-lockedloop circuit (hereinafter referred to as a PLL circuit) composed of aphase comparator 1, a low-pass filter (hereinafter referred to as anLPF) 2, a voltage-controlled oscillator (hereinafter referred to as aVCO) 3, and a frequency divider 4. To the video switchover detectioncircuit, an external HS obtained by extracting and shaping a horizontalsynchronization signal for a video signal and an external VD obtained byextracting and shaping a vertical synchronization signal are input. Asinput signals for detecting vide switchover, a horizontalsynchronization signal and a vertical synchronization signal, or anexternal HD and external VD are used.

[0028] As an H system for detecting out of lock in the horizontalsynchronization signal, the video switchover detection circuit comprisesa reset signal generating circuit 5, a first counter 6 for counting theoutput pulse of the VCO 3, a decision value setting circuit 7, and adecision circuit 8. The decision value setting circuit 7 and thedecision circuit 8 compose a horizontal synchronization decision section9 equivalent to horizontal synchronization decision means fordetermining the lock state of a horizontal synchronization signal basedon the count value of the first counter 6. As a V system for detectingout of lock in the vertical synchronization signal, the video switchoverdetection circuit comprises a reset signal generating circuit 10, asecond counter 11 for counting the internal HD of the frequency divider4, a decision value setting circuit 12, and a decision circuit 13. Thedecision value setting circuit 12 and the decision circuit 13 compose avertical synchronization decision section 14 equivalent to verticalsynchronization decision means for determining the lock state of avertical synchronization signal based on the count value of the secondcounter 11. Further provided is an output circuit 15 equivalent todetection output means composed of an OR (logical conjunction) circuitfor outputting as video switchover detection signals the outputs of thehorizontal synchronization decision section 9 and the verticalsynchronization decision section 14.

[0029] To one input terminal of the phase comparator equivalent to phasecomparison means, the internal HD obtained by multiplying the outputoscillating signal of the VCO 3 by 1/N by the frequency divider 4 isinput as a reference signal. To the other input terminal, an external HDhat is based on the horizontal synchronization signal for a video signalis input. The phase comparator compares the phase of the internal HDwith that of the external HD and outputs an error signal that goesactive (for example HIGH level) when the phases differ with each other.The phase comparator 1 may be composed using a comparator or an EX-OR(exclusive OP) circuit. The frequency divider 4 is composed of forexample a program counter.

[0030] The reset signal generating circuit 5 generates a reset signalbased on the internal HD and the oscillating signal of the VCO 3(hereinafter referred to as an output pulse) and outputs the resetsignal to the reset terminal of the first counter 6. The first counter 6equivalent to phase difference count means is adapted so that an errorsignal from the phase comparator 1 is input to the enable terminal, areset signal from the reset signal generating circuit 5 is input to thereset terminal, and an output pulse from the VCO 3 is input to the clockterminal. In each horizontal period, when the reset signal from thephase comparator 1 goes active, the output pulse of the VCO 3 is countedonly for the active period.

[0031] In the horizontal synchronization decision section 9, thedecision value setting circuit 7 sets in advance a decision value usedto determine whether the horizontal synchronization signal is out ofsynchronization (PLL circuit is out of lock). The decision circuit 8monitors the count value of the first counter 6 and, when the countvalue has exceeded the decision value, outputs an out-of-lock detectionsignal.

[0032] The reset signal generating circuit 10 generates a reset signalbased on the internal HD and external VD and outputs the reset signal tothe reset terminal of the second counter 11. The second counter 11equivalent to horizontal synchronization count means is adapted so thatthe reset signal from a reset signal generating circuit is input to thereset terminal and an internal HD is input to the clock terminal, andthe internal HD is counted after reset in each vertical period. In thevertical synchronization decision section 14, the decision value settingcircuit 12 sets in advance a decision value used to determine whetherthe vertical synchronization signal is out of synchronization. Thedecision circuit 13 monitors the count value of the second counter 11and, when the external VD is input at a count value smaller than thedecision value, outputs an out-of-lock detection signal. The resetsignal generating circuits 5 and 10 may be composed using a one-shotmulti-circuit.

[0033] The output circuit 15 outputs as a video switchover detectionsignal the out-of-lock detection signal output from the horizontalsynchronization decision section 9 or vertical synchronization decisionsection 14. The output circuit 15 may use an AND (logical conjunction)circuit instead or an OR circuit to simultaneously perform phasedislocation detection in the horizontal and vertical directions.

[0034] Operation of the video switchover detection circuit in theembodiment will be described. First, the out-of-lock detection operationin the H system will be described referring to FIG. 2. In FIG. 2, (A)shows the lock state of the horizontal synchronization signal while (B)shows the out-of-synchronization state (unlock state) of the horizontalsynchronization signal.

[0035] The external HD that is based on the horizontal synchronizationsignal for the video signal is input to the phase comparator 1 and itsphase is compared with that of the internal HD. In case the phases ofthe two input signals in the phase comparator 1 are not dislocatedsignificantly from each other, the PLL circuit composed of the phasecomparator 1, LPF 2, VCO 3 and frequency divider 4 is in the lock stateand maintains a closed loop. In this case, from the phase comparator 1an error signal ES with small time width is output with a short-intervaltiming as shown in FIG. 2(A). In FIG. 2, the output pulse of the VCO 3is shown as a clock. In the reset signal generating circuit 5, a resetsignal is generated with a predetermined clock timing at the trailingedge of the internal HD. This reset signal resets the first counter 6.

[0036] When the output of the phase comparator 1 is asserted and theerror signal ES is output, the first counter 6 starts counting theoutput pulse of the VCO 3. While the error signal ES is active, thecount value of the first counter 6 is incremented. In the horizontalsynchronization decision section 9, the decision value of the decisionvalue setting circuit 7 is set to approximately the maximum value (NH)in the range where the PLL circuit is locked. In this practice, thecount value NX1 of the first counter is compared with the decision valueNH with the timing at the leading edge of the external HD in thedecision circuit 8. When NX1 is smaller than NH (NX1<NH), the phasedifference between the external HD and the internal HD is small so thatthe PLL circuit is assumed as locked and the out-of-lock signal is notoutput. As a result, the video switchover detection signal is not outputfrom the output circuit 15.

[0037] On the other hand, in case the horizontal synchronization signalbecomes out of synchronization and the phase difference between the twoinput signals in the phase comparator 1 gets larger, from the phasecomparator 1 an error signal ES with large time width is output with along interval in which the phases differ from each other, as shown inFIG. 2(B). In this practice, same as the aforementioned case of the lockstate, the first counter 6 starts counting the output pulse of VCO 3 andthe count value NX is compared with the decision value NH with thetiming at the leading edge of the external HD. The count value NX inthis case is larger than the count value NH (NX1>NH), so that the phasedifference between the external HD and the internal HD is large and thePLL circuit is assumed as out of lock and the out-of-lock signal isoutput. As a result, the video switchover detection signal is outputfrom the output circuit 15 and out of lock in the horizontalsynchronization signal is detected.

[0038] In this case, it suffices that the first counter 6 can count upto the count value (NH) large enough to detect out of lock. Thus acapacity of 3 or 4 bits of the first counter 6 is sufficient.

[0039] While the aforementioned example shows a case where the phase ofthe external HD is delayed behind the phase of the internal HD, an errorsignal is output likewise in case the phase of the external HD isadvanced beyond the phase of the internal HD. Thus the operation isquite the same and corresponding description is omitted.

[0040] Next, the out-of-lock detection operation in the V system will bedescribed referring to FIG. 3. In FIG. 3, (A) shows the lock state ofthe vertical synchronization signal while (B) shows theout-of-synchronization state (unlock state) of the verticalsynchronization signal.

[0041] In the reset signal generating circuit 10, a reset signal isgenerated with the predetermined timing at the trailing edge of theinternal HD that is based on the vertical synchronization signal for avideo signal after the external VD has been deasserted, or with thetiming at the leading edge of the external VD. This reset signal resetsthe second counter 11. The second counter 11 counts the internal HD(number of horizontal scanning lines in the video signal: Line n). Inthe vertical synchronization decision section 14, the counter value ofthe second counter 11 obtained when the external VD is deasserted iscompared with the decision value of the decision value setting circuit12. In this practice, the decision value NV of the decision valuesetting circuit is set to a count value (NV=525 assuming the NTSC systemvideo signal) obtained in case the vertical synchronization signal is inthe lock state.

[0042] When the vertical synchronization signal is in the lock state,the external VD is deasserted with a substantially normal timing againstthe internal HD, that is, between Line 525 and Line 1 of the nextvertical period. In this case, the counter value matches the decisionvalue in the second counter 11 so that synchronization with the verticalsynchronization signal is assumed in the decision circuit 13. Theout-of-lock signal is not output from the decision circuit 12 and thevideo switchover detection signal is not output from the output circuit15.

[0043] On the other hand, in case the external VD is deasserted earlierthan the predetermined timing as in FIG. 3(B), the count value of thesecond counter 11 is smaller than the decision value and different fromthe decision value. This figure shows a case where the external VD isdeasserted when the count value is 320. In this case, in the decisioncircuit 13, it is assumed that the vertical synchronization signal isplaced out of synchronization (unlock state) in the middle of thescanning in the vertical direction. The out-of-lock signal is outputfrom the decision circuit 13 and the video switchover detection signalis output from the output circuit 15. Then out of lock in the verticalsynchronization signal is detected.

[0044] While the foregoing description assumes the point in time thecounter value of the second counter 11 is 525 with the timing of thetrailing edge of the external VD for simplicity, the lock state may bedetermined within a practical range including the case where theexternal VD is deasserted with a slight difference in time, in thevertical blanking period.

[0045] As mentioned earlier, in this embodiment, The counter in the Hsystem counts the output pulse (clock) of the VCO in the period theerror signal of the output of the phase comparator is active and out oflock is detected based on the magnitude of the phase difference betweenthe internal HD (reference signal) and the external HD. This reduces thecircuit scale of the counter and setting circuit as well as making itpossible to detect out of synchronization of the horizontalsynchronization signal by using a small-scale counter. In the V system,the counter counts the internal HD and out of lock is detected based onthe count value at the trailing edge of the external VD, that is, theinput timing of the external VD against the internal HD (referencesignal). This allows detection of out of synchronization of the verticalsynchronization signal by using a simple circuit comprising asmall-scale counter. Through detection of out-of-lock state in at leastone of the H system and the V system, it is possible to easily andsecurely switch over a video signal.

[0046] Decision of the count value to detect out of lock may be madewith the timing the external HD is asserted in relation to the internalHD in the H system and with the timing the external VD is asserted inthe V system. This reduces the time required for counting thusdecreasing the detection time for video switchover.

[0047] According to the embodiment, it is possible to detect switchoverof video signals with high accuracy and at a high speed throughdetection of the lock state of a horizontal or vertical synchronizationsignal, by using a small-scale simple circuit configuration, without thecircuit configuration being complicated and upsized. Combination ofout-of-lock detection in the H system and out-of-lock detection in the Vsystem provides more secured and higher-accuracy detection of videosignal switching.

[0048]FIG. 4 is a block diagram showing the exemplary configuration ofvideo monitoring apparatus as an application example of a video signalswitchover detection circuit according to this embodiment. In the videomonitoring apparatus, outputs of video cameras 21, 22, 23 installed in aplurality of locations are connected to video switchover apparatus 24.To the video switchover apparatus 24 a monitor 25 and video recordingapparatus 26 are connected. The video switchover apparatus 24 isinternally or externally equipped with video switchover detectionapparatus 20 and motion detection apparatus 27.

[0049] Video signals shot and output by a plurality of video cameras 21,22, 23 are switched over as required by the video switchover apparatus24 and output to the monitor 25 and displayed as a picture or sent tothe video recording apparatus 26 for recording. The motion detectionapparatus 27 detects the motion in each video signal and outputs amotion detection signal. The video switchover detection apparatus 20detects that the video signals from the video cameras are switched over.

[0050] In the video monitoring apparatus, any motion in the picture shotin each location is assumed as an abnormality such as presence of aninvader. Thus, the motion detection apparatus 27 is used to, forexample, issue an alarm from the video switchover apparatus 24 or acontroller (not shown) depending on the output of the motion detectionsignal. However, the motion detection signal may be inadvertently outputfrom the motion detection apparatus 27 when video signals are switchedover. This can be prevented by halting the motion detection in themotion detection apparatus 27 for a predetermined period in case videosignal switchover is detected, by using video switchover detectionapparatus 20 comprising video switchover detection circuit according tothe invention. In this case, it is possible to detect video signalswitchover with high accuracy and at a high speed by way of asmall-scale and simple circuit configuration, so that the configurationin this embodiment is considerable advantageous.

INDUSTRIAL APPLICABILITY

[0051] As mentioned earlier, according to the invention, it is possibleto provide a video switchover detection circuit that reduces the circuitscale and allows high-accuracy detection with a smaller-scaleconfiguration.

1. A video switchover detection circuit comprising a phase-locked loopcircuit for comparing the phase of an input signal with that of anoscillating signal that is based on the input signal to perform phasesynchronization, said video switchover detection circuit detectingswitchover of input video signals by using a synchronization signal fora video signal used as said input signal and a reference signal that isbased on said oscillating signal, said video switchover detectioncircuit comprising: phase comparison means for comparing the phase of ahorizontal synchronization signal for said video signal with that ofsaid reference signal; phase difference count means for starting tocount time when a phase difference has occurred between both signalsbased on said phase comparison results and counting the period in whichthe phase difference persists; horizontal synchronization decision meansfor determining out of synchronization of said video signal in thehorizontal direction in case the count value has exceeded apredetermined decision value based on the count value of said phasedifference count means; and detection output means for outputting avideo switchover detection signal indicating switchover of video signalsbased on the output of said horizontal synchronization decision means.2. A video switchover detection circuit according to claim 1, whereinsaid phase comparison means outputs an error signal that goes active andindicates phase dislocation when the phase of a horizontalsynchronization signal for said video signal differs from that of saidreference signal and that said phase difference count means counts theclock of said oscillating signal in the period in which the error signalis active thus counting the period in which phase difference persistswhen said error signal is input to the enable terminal.
 3. A videoswitchover detection circuit according to claim 1, further comprising:horizontal synchronization count means for counting the reference signalcorresponding to the horizontal synchronization signal for said videosignal; and vertical synchronization decision means for determining outof synchronization of said video signal in the vertical direction basedon the count value of said horizontal synchronization count means incase the count value obtained when the vertical synchronization signalfor said video signal is input is below a specified decision value,wherein said detection output means outputs a video switchover detectionsignal indicating switchover of video signals based on the output ofsaid horizontal synchronization decision means and said verticalsynchronization decision means.
 4. A video switchover detection circuitcomprising a phase-locked loop circuit for comparing the phase of aninput signal with that of an oscillating signal that is based on theinput signal to perform phase synchronization, said video switchoverdetection circuit detecting switchover of input video signals by using asynchronization signal for a video signal used as said input signal anda reference signal that is based on said oscillating signal, said videoswitchover detection circuit comprising: horizontal synchronizationcount means for counting the horizontal synchronization signal for saidvideo signal; vertical synchronization decision means for determiningout of synchronization of said video signal in the vertical directionbased on the count value of said horizontal synchronization count meansin case the count value obtained when the vertical synchronizationsignal for said video signal is input is below a specified decisionvalue; and detection output means for outputting a video switchoverdetection signal indicating switchover of video signals based on theoutput of said vertical synchronization decision means.